1.   高性能忆阻卷积神经网络容错设计技术，国家自然科学基金面上项目(62074055),2021.01~2024.12，主持。

2.   低功耗限制下VLSI电路的低费用确定性测试研究，国家自然科学基金面上项目（60673085），2007.1~2009.12, 主持。

3.    教育部新世纪优秀人才支持计划（NCET-12-0165）,2013.1~2015.12, 主持。

4.     忆阻神经网络可靠性设计方法研究，湖南省自然科学基金资助项目（2018JJ2064），2018.1~2020.12, 主持。

5.    降低全扫描设计VLSI电路低测试功耗，低测试应用时间方法硬件开销的研究（教育部留学回国人员科研启动基金项目），2008.1~2009.12, 主持。

6.    《深度学习发展历程与实践》课程内容建设，教育部产学合作协同育人项目(企业合作方：百度公司)，2019.5~2020.5, 主持。

7.  集装箱箱号识别深度学习方法设计与实现，横向项目，2020.1~2020.12, 主持。

8. 智能防御式平台软件系统的前台编码和UI设计，横向项目，2019.3~2019.4, 主持。

9. 非易失性CMOS忆阻器及其构成的计算存储融合可重构交叉阵列架构，国家自然科学基金委员会，重大研究计划培育项目(91964108),2020.1~2022.12，参加。

10. 拆分测试集到芯片与测试仪上的新技术，国家自然科学基金面上项目（61472123），2015.1~2018.12,参加。

11. 异步无线传感器网络环境下的数据压缩关键技术，国家科技部863计划项目(2006AA01Z227)，2006.12~2008.12, 参加。

12. 由被测电路自己产生测试向量的内建自测试技术研究，国家自然科学基金资助项目（60773207），2008.1~2010.12, 参加.

本科生：深度学习发展历程与实践、多元统计分析

研究生：深度学习方法

留学生：Integrated Circuit Design

[1] Melnyk P, You Z, Li K. A high-performance CNN method for offline  handwritten Chinese character recognition and visualization, Soft Comput, 30  May 2019 (online). https://doi.org/10.1007/s00500-019-04083-3.

[2] 胡飞，尤志强，刘鹏，邝继顺，基于忆阻器交叉阵列的卷积神经网络电路设计，计算机研究与发展，2018, 55(5): 1097-1107.

[3] Yan Chen, Zhiqiang You, Yingjie Zhang, Jishun Kuang and Jing  Zhang, “A Novel Memristor-Based Restricted Boltzmann Machine for Contrastive  Divergence,” IEICE Electronics Express, vol. 15, no.2, Pages 20171062, Jan. 2018.

[4] Peng Liu, Zhiqiang You, Jishun Kuang, Michael Elimu, Shuo Cai and  Weizheng Wang, “Logic operation-based Design for Testability method and  parallel test algorithm for 1T1R crossbar.” Electronics Letters 53(25):  1631-1632, 2017.

[5] Zhiqiang You, Fei Hu, Liming Huang, et al. "A long  lifetime, low error rate RRAM design with self-repair module," Journal  of Semiconductors,2016,37(11):115004-5

[6] Peng Liu, Zhiqiang You, Jishun Kuang, Zhipeng Hu, Heng Duan and  Weizheng Wang, "Efficient March test algorithm for 1T1R cross-bar with  complete fault coverage." Electronics Letters 52(18): 1520-1522, 2016.

[7] PengLiu, Zhiqiang You, Jishun Kuang, Zhipeng Hu,Weizheng Wang, “Logic operation-basedDFT method and 1R memristive crossbar march-like test algorithm,” IEICEElectronics Express, vol. 12, no.23, pp20150839, Dec. 2015.

[8] Weiwei Wang, Zhiqiang You,Peng Liu, Jishun Kuang, “An adaptive neural network A/D converter based on CMOS/memristor hybriddesign,”IEICE Electronics Express, vol. 11, no. 24, pp. 20141012, Dec. 2014.

[9] BoshengLiu, Zhiqiang You, Xiangrao Li, Jishun Kuang, and Zheng Qin, “Comparator andHalf Adder Design Using Complementary Resistive Switches Crossbar,” IEICEElectronics Express, vol. 10, no. 13, p. 20130369, Jul. 2013.

[10] ZhiqiangYou, Weizheng Wang, Peng Liu, Jishun Kuang, Zheng Qin, “A scan disabling-basedBAST scheme for test cost and test power reduction,” IEICE Electronics Express,vol.9, no. 2, 111-116, 2012.

[11] 尤志强，彭福慧，邝继顺，张大方．一种基于BFT型拓扑结构片上网络低费用测试方法，电子学报2011,39（11）：2663-2669.

[12] ZhiqiangYou,WeizhengWang, Zhiping Dou,Peng Liu, Jishun Kuang,“A scan disabling-basedBASTscheme for test cost reduction”,IEICE Electronics Express, vol.8, no. 16, 1367-1373, 2011.

[13] ZhiqiangYou, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara, “Capture in TurnScan for Reduction of Test Data Volume, Test Application Time and Test Power” IEEE Proc. ATS,2010, 371-374.

[14] Zhiqiang You, Jiedi Huang,Jishun Kuang, Michiko Inoue, Hideo Fujiwara, A Response Compactor for ExtendedCompatibility Scan Tree Construction, IEEE Proc. ASICON, pp.609-612, 2009.

[15] 成永升，尤志强，邝继顺．扩展相容性扫描树中的测试响应压缩器设计，计算机辅助设计与图形学学报，2009，21(4): 500-504.

[16] Gui Dai, Zhiqiang You, Jishun Kuang, Jiedi Huang,“DCScan: A Power-AwareScan Testing Architecture” IEEE Proc. ATS,2008, 343-348.

[17] Yongsheng Cheng, Zhiqiang You,  Jishun Kuang,“Test Response Data Volume and Wire Length Reductions for ExtendedCompatibilities Scan Tree Construction”, 4^th IEEE International Symposium on Electronic Design, Test &Applications(DELTA’2008),pp. 308-313, Jan. 2008.

[18] Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue and Hideo Fujiwara, “A low power deterministic test using scan chain disable technique,” IEICE Trans. on Information & Systems, Vol. E89-D, No. 6, pp.1931-1939, Jun. 2006.

[19] Zhiqiang You, Michiko Inoue, Hideo Fujiwara, “Extended Compatibilities for Scan Tree Construction”, Digest of papers,11th IEEE European Test Symposium (ETS06), pp. 13-18, May 2006.

[20] Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir and Hideo Fujiwara , “Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths”. IEICE Trans. on Information & Systems, Vol. E88-D, No. 8, pp.1940-1947, Aug. 2005.

[21] Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara, “A Low Power Deterministic Test Using Scan Chain Disable Technique”, IEEE 6th Workshop on RTL and High Level Testing (WRTLT’05), pp.184-191, July 2005.

[22] Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir and Hideo Fujiwara, “Power-constrained test scheduling for RTL datapaths of non-scan BIST schemes”. IEEE Proc. ATS, 2004.32-39.

[23] Zhiqiang You, Michiko Inoue and Hideo Fujiwara, "On the non-scan BIST schemes under power constraints for RTL data paths," IEEE 4th Workshop on RTL and High Level Testing (WRTLT'03), pp.14-21, Nov. 2003.

[24] 尤志强, 张大方. 数据等概率分档排序算法的定量研究. 计算机学报. 2003, 26(1): 45-50.

[25] KUANG JiShun, YOU ZhiQiang, ZHU Qijian, MIN Yinghua. IDDT : Fundamentals and Test Generation. Journal of Computer Science & Technology, 2003, 18(3): 299-307.

[26] 尤志强, 张大方, 刘先霞. 基于布尔过程论的波形和波形空间的性质及应用. 电子学报. 2000, 28(8): 107-109.