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中文名: 王奕
职称: 助理教授
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[1] Yi Wang, Renfa Li, “FPGA basedUnified Architecture for Public Key and Private Key Cryptosystems[J]”, Frontiers of Computer Science,Vol 7, Issue 3, pp. 307-316, Jun 2013.

[2] Thi Hanh Nguyen,Yi Wang, Yajun Ha and Renfa Li, “Improved Chaff Point Generation for VaultScheme in Bio-Cryptosystems[J]”, IET Biometrics, Vol 2, Issue 2, pp. 48-55, Jun 2013.

[3] Thi Hanh Nguyen, YiWang and Renfa Li, “An Improved Ridge Features Extraction Algorithm forDistorted Fingerprint Matching[J]”, Elsevier, Journal of Information Security and Applications2013. Available online: http://dx.doi.org/10.1016/j.jisa.2013.11.001

[4] TranBichThuan Pham, YiWang, Renfa Li, ”Designing one-bit Full-Adder/Subtractor based onMultiplexer and LUT’s architecture on FPGA[J]”  International Journal of Digital Content Technology and its Applications,Vol 7, Issue 8, pp. 455-464. Apr 2013.

[5] TranBichThuan Pham, YiWang, Renfa Li, “A novelty method to accelerate dual-precisionfloating-point multiplier[J]” AJEEE: Australian Journal of Electrical & Electronics Engineering,2013 (accepted)

[6] Yi Wang,Douglas L. Maskell, Jussipekka Leiwo, “A Unified Architecture for A Public KeyCryptographic Coprocessor[J]” Journal of Systems and Architecture, issue 54, pages 1004-1016,2008.

[7] 李志灿,王奕,李仁发“可重构Gr?stl设计研究及其FPGA实现[J]”《计算机工程与应用》,第48卷,第6期,49-52页, 2012

[8] 周权,王奕,李仁发 "基于FPGA的可重构JH算法的设计与实现[J]" 《计算机工程》,第38卷,第11期,208-210页, 2012

[9] 吴武飞,王奕*,李仁发“可重构KECCAK算法设计及FPGA实现[J]”《计算机应用》,第32卷,第3期,864-866页, 2012

[10] 周权,王奕,李仁发 " RFID系统中低功耗JH算法的设计与实现J]" 《小型微型计算机系统》,第34卷,第8期,1944-1948页, 2013

[11] 李志灿,王奕,沈航,李仁发,赵伟“轻量级加密算法的低功耗硬件实现与研究”,《小型微型计算机系统》,第34卷,第11期,2574-2578页,2013



 [12]Tranbichthuan Pham, YiWang, Renfa Li, “A Variable-latency Floating-point Division in Associationwith Predicted Quotient and Fixed Remainder” IEEE International MidWestSymposium on Circuit and System, Ohio, USA, pp.1240-1245, 2013

[13]Thi Hanh Nguyen, YiWang, Trung Nhan Nguyen, Renfa Li,” A Fingerprint Fuzzy Vault Scheme UsingA Fast Chaff Point Generation Algorithm” 2013 IEEE InternationalConference on Signal Processing, Communications and Computing (ICSPCC 2013),pp.1-6, 2013.

[14]Zemin Cai, Yi Wang and Renfa Li “AnImproved Differential Fault Analysis Attack to AES Using Reduced SearchingSpace” CSS 2013, LNCS 8300, pp. 441-449, 2013.

[15] Wei Zhao, Yi Wang, Renfa Li. “A Unified Architecture for DPA-resistantPRESENT[C]”, The 8th InternationalConference on Innovations in Information Technology, UAE, pp. 244-248, March, 2012.

[16] Juanli Zeng; Yi Wang,Cheng Xu; Renfa Li. “Improvement on Masked S-box Hardware Implementation[C]” The 8th International Conference onInnovations in Information Technology,UAE, pp. 113-116, March, 2012.

[17] Yi Wang, Renfa Li,”A Unified Architecture for SupportingOperations of AES and ECC[C]”, PAAP2011 The 4th International Symposium on Parallel Architectures, Algorithmsand Programming, pp. 185-189, Dec, 2011.

[18] Yi Wang,Zheng Yuan, Renfa Li, “Secret Sharing based Countermeasure for AES S-Box[C]”13th International Symposium on Integrated Circuits, Dec, pp. 504-507, 2011.

[19] Qian Song, Yi Wang*, Zhican Li, Quan Zhou,Wufei Wu and Renfa Li, “FPGA basedOptimized SHA-3 Finalist in Reconfigurable Hardware[C]” 13th InternationalSymposium on Integrated Circuits,  pp.508-511, Dec, 2011.

[20] Zheng Yuan, Yi Wang, Jing Li, Renfa Li, Wei Zhao “ FPGA based Optimization for MaskedAES Implementation[C]” , IEEE InternationalMidwest Symposium on  Circuit and Systems2011, pp. 1-4, Aug, 2011.

[21] Francesco Regazzoni, Yi Wang, Francois-Xavier Standaert,“FPGA Implementations of the AES Masked Against Power Analysis Attacks[C]”, 2ndInternational Workshop on Constructive Side-Channel Analysis and Secure Design,Germany, 2011.

[22] Yi Wang,Douglas L. Maskell, “AUnified Signed-digit Adder for High-radix Modular Exponentiation on GF(p)and GF(2p)[C]” InternationalSymposium on Integrated Circuit, (ISIC), pp.687-690,2009.

[23] Yi Wang,Douglas L. Maskell, “A Robust Algorithmfor DPA-resistant ECC[C]” International Symposium on Integrated Circuit, (ISIC), pp. 667-670, 2009.

[24] Yi Wang, Douglas L. Maskell,Jussipekka Leiwo and Thambipillai Srikanthan, “Unified Signed-Digit NumberAdder for RSA and ECC Public-key Cryptosystems[C]”, IEEE Asia Pacific Conference on Circuits andSystem (APCCAS), pp. 1655 – 1658, Dec., 2006.

[25] Yi Wang, Jussipekka Leiwo,Thambipillai Srikanthan, Luo Jianwen, “An Efficient Algorithm for DPA-resistentRSA[C]”, IEEEAsia Pacific Conference on Circuits and System, APCCAS, pp.1659-1662, Dec., 2006.

[26] Yi Wang, Jussipekka Leiwo,Thambipillai Srikanthan, Yu Yu, “FPGA based DPA-resistant UnifiedArchitecture for Signcryption[C]”, ThirdInternational Conference on  Information Technology: New Generations, ITNG 2006, pp. 571 – 572, Apr., 2006.

[27] 安建峰,樊晓亚,张盛兵,王党辉,王奕, “VMSIM: Virtual Machine Based a Full System SimulationPlatform for Microprocessors’ Functional Verification[C]”,Third International Conference on  Information Technology: New Generations, ITNG 2006, pp. 571 – 572, Apr., 2006.

[28] Yi Wang, Jussipekka Leiwo,Thambipillai Srikanthan, “A unified architecture for crypto-processingin embedded systems[C]”, SecondInternational Conference on Embedded Software and Systems, pp. 37 - 43, Dec., 2005.

[29] Yi Wang, Jussipekka Leiwo,Thambipillai Srikanthan, “Efficient High Radix Modular Multiplication forHigh-speed Computing in Re-configurable Hardware[C]”, IEEE International Symposium on Circuits andSystems (ISCAS),pp., 1226 – 1229, May, 2005.